Referring to FIG. 1, a system on a chip (SOC) 105 according to the conventional art is shown. The SOC is typically an application specific integrated circuit (ASIC). As depicted in FIG. 1, a memory controller 110 is an integral part of most SOCs 105. The memory controller 110 provides for transfer of data between an external memory unit 115 and the SOC 105.
The memory unit 115 is coupled to the memory controller 110 by an address bus 120, a data bus 125, and a plurality of control lines 130. Typically, the memory unit 115 comprises an array of memory cells arranged in a plurality of banks 135-138. A bank decoder 145 provides for decoding a first portion of lines of the address bus, to select one of the plurality of banks 135-138. A row decoder 150 provides for decoding a second portion of lines of the address bus, to select one of a plurality of rows within the selected bank 135-138. A column decoder 155 provides for decoding a third portion of lines of the address bus to select one of a plurality of columns within the selected bank 135-138.
Depending upon the SOC 105, application bandwidth requirements and operating conditions, a variety of external memory units 115 are deployed. For example, the memory unit 115 may be a single data rate (SDR) or double data rate (DDR) type SDRAM. The memory unit may comprise 2, 4, 8, 16, or more banks. The data bus 125 of the memory unit 115 may comprise 16, 32, 64, 128 or more signal lines. The memory unit 115 may support burst data transfer, wherein the burst length may be 2, 4, 8, 16 or more words or the like. The memory unit may also be any one of several speed grades.
The memory controller 110 implements a protocol for transferring data to and from the memory unit in accordance with the requirements of the type of memory unit 115 and/or requirements of the vendor of the memory unit 115. For example, in order to transfer data to or from an SDRAM, before any read or write commands can be issued to a bank 135-138, a row in that bank 135-138 has to be opened. This is accomplished with one or more activate (ACT) commands which selects the bank 135-138 and the row to be activated. After the row is opened with an ACT command, a read or write command may be issued to the column, subject to timing specific ACT to CAS timing constraints. Once a bank 135-138 is opened with an ACT command, it must be closed with a precharge (PRE) command, before a different row in the same bank can be opened (e.g., activated).
There are several timing constraints that have to be satisfied for access to the memory unit 115. Table 1 shows exemplary timing constraints for a synchronous dynamic random access memory (SDRAM).
TABLE 1@ 133 MHzConstraintSymbolMinMaxUnit(tCK = 7.5 ns)Activate (RAS) toTRAS45120000ns6 ClockPrecharge (PRE)Activate (RAS) toTRC65ns9 ClockActive/AutoRefreshActivate (RAS) toTRCD20ns3 ClockRead/Write (CAS)Precharge (PRE)TRP20ns3 Clockto Activate (RAS)Activate (RAS)TRRD15ns2 ClockBank A toActive (RAS)Bank BWrite RecoveryTWR15ns2 ClockTimeInternal Write toTWTR1tCK1 ClockRead Command DelaySome of the timing constraints are dependent on the clock speed of the SDRAM and others based on the SDRAM vendor's specifications.
Referring now to FIG. 2, an exemplary sequence of transfers according to the convention art is shown. The exemplary series of transfers is based upon a synchronous dynamic random access memory (SDRAM) operating in double data rate (DDR) mode, having four banks and supporting a burst size of 4. As illustrated in FIG. 2, the first transfer comprises writing 8 words to Bank 0 (B0) the second, third and fourth transfers each comprises a write of 2 words to Banks 1, 2 and 3 (B1, B2, B3) respectively.
The row of the bank to which the data is to be written is opened (e.g., activated) upon initiation of a transfer. The data is then transferred by activating the applicable row of the bank. The bank is then closed upon completion of the transfer to the bank. The various commands are issued according to timing constraints of the applicable protocol of the memory unit.
For example, a row access command (RASB0) and four column access commands (CASB0) are issued to transfer the eight words (W1B0-W8B0) to Bank 0, between clock cycles 0-11. Bank 0 is then closed by a precharge command PREBO. One row access command (RASB1) and one columns access command (CASB1) are issued to transfer the second page packet to Bank 1, between clock cycles 15-20. Bank 1 is then closed by a precharge command (PREB1). One row access command (RASB2) and one column access command (CASB2) are issued to transfer the third page packet to Bank 2, between clock cycles 24-29. Bank 2 is then closed by a precharge command (PREB2). One row access command (RASB3) and one column access command (CASB3) are issued to transfer the fourth page packet to Bank 3, between clock cycles 33-38. Bank 3 is then closed by a precharge command (PREB3).
The exemplary series of write transfers consumes 40 clock cycles. A substantial number of the clock cycles are not utilized to issue access commands and/or write the data. Therefore, the bandwidth of the SDRAM is not utilized efficiently.
Furthermore, depending upon the SOC platform and applications, the memory interface controller may have to support various data access patterns. For example, the memory interface controller may need to support simple linear access for video scan line fetch or a complex 2D access for MPEG applications. For each such data access pattern, the memory interface controller has to map the logical address to the physical address (bank, row, column, chip-select) such that the external SDRAMs can understand. Thus, the memory interface controller has to support a variety of logical to physical address mappings based on internal bus commands and external memory configurations.
The memory controller should also be parameterizable for different configurations. For example, low-end cost conscious applications such as consumer DVDs, where a low pin count is important, lower interface widths are common. For high-end graphics applications that require high memory bandwidth, high interface widths are common.